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86
CY7C186
8Kx8 Static RAM
Features
* High speed -- 20 ns * Low active power -- 605 mW * Low standby power -- 110 mW * CMOS for optimum speed/power * Easy memory expansion with CE1, CE2, and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. The device has an automatic power-down feature (CE1), reducing the power consumption by over 80% when deselected. The CY7C186 is in a 600-mil-wide PDIP package and a 32-pin TSOP (std. pinout). An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
The CY7C186 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is
LogicBlock Diagram
Pin Configuration
DIP Top View
NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE CE 2 A3 A2 A1 OE A0 CE 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
I/O0 INPUT BUFFER I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5 I/O6 CE1 CE2 WE OE
POWER
A1 A2 A3 A4 A5 A6 A7 A8
ROW DECODER
256 x 32 x 8 ARRAY
COLUMN DECODER
DOWN
I/O7
10
A
A
A
A
Selection Guide[1]
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Notes: 1. For military specifications, see the CY7C186A datasheet.
A
12
11
0
9
7C186-20 20 110 20/15
7C186-25 25 100 20/15
7C186-35 35 100 20/15
Cypress Semiconductor Corporation Document #: 38-05280 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised March 22, 2002
CY7C186
Pin Configurations (continued)
TSOP Top View OE A1 A2 A3 CE2 WE VCC NC NC NC A4 A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 21 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC GND I/O2 I/O1 I/O0 A12 A11 A10
C186-3
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ............................................ -0.5V to +7.0V DC Input Voltage[2] ........................................ -0.5V to +7.0V Range Commercial Ambient Temperature 0C to +70C VCC 5V 10% Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Electrical Characteristics Over the Operating Range
7C186-20 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE1 Power-Down Current Automatic CE1 Power-Down Current GND < VI < VCC VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA Max. VCC, CE1 > VIH, Min. Duty Cycle=100% Max. VCC, CE1 > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Output Leakage Current GND < VI < VCC, Output Disabled Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -5 -5 Min. 2.4 0.4 VCC 0.8 +5 +5 -300 110 20 15 2.2 -0.5 -5 -5 Max. 7C186-25,35 Min. 2.4 0.4 VCC 0.8 +5 +5 -300 100 20 15 Max. Unit V V V V A A mA mA mA mA
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 7 7 Unit pF pF
Notes: 2. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05280 Rev. **
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CY7C186
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R1 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R1 481 ALL INPUT PULSES 3.0V R2 255 GND 10% 90% 90% 10%
R2 255
5 ns
5 ns
(a)
(b)
THEVENIN EQUIVALENT OUTPUT 167 1.73V
Switching Characteristics Over the Operating Range[5]
7C186-20 Parameter READ CYCLE tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD WRITE tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6] CE1 LOW to Low Z
[7]
7C186-25 Min. 25 Max.
7C186-35 Min. 35 Max. Unit ns 35 5 35 35 15 3 10 5 3 ns ns ns ns ns ns ns ns ns 10 0 ns ns 20 35 20 20 25 0 0 20 12 0 ns ns ns ns ns ns ns ns ns ns 8 5 ns ns
Description
Min. 20
Max.
20 5 20 20 9 3 8 5 3 8 0 20 20 15 15 15 0 0 15 10 0 7 5 5 25 20 20 20 0 0 15 10 0 0 5 3 3 5
25 25 25 12 10
CE2 HIGH to Low Z CE1 HIGH to High Z[6, 7] CE2 LOW to High Z CE1 LOW to Power-Up CE1 HIGH to Power-Down CYCLE[8] Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z
[6]
10
20
7
Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All signals must be active to initiate a write, and any signal can terminate a write by going inactive. The data input set-up and hold timing should be referenced to the trailing edge of the signal that terminates the write.
Document #: 38-05280 Rev. **
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CY7C186
Switching Waveforms
Read Cycle No. 1[9]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2[10, 11]
CE1 tRC
CE2 OE OE
tACE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE
tDOE
tHZOE
tHZCE
HIGH IMPEDANCE
DATA VALID
VCC SUPPLY CURRENT
tPU 50%
tPD ICC 50% ISB
Write Cycle No. 1 (WE Controlled)[11, 12]
tWC ADDRESS CE1 tAW CE2 CE WE tSA tSCE2 tPWE tSCEI t HA
OE tSD DATA I/O NOTE 13 tHZOE
Notes: 9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. 10. WE is HIGH for read cycle. 11. Data I/O is High Z if OE = VIH, CE1 = VIH, or WE = VIL. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. During this period, the I/Os are in the output state and input signals should not be applied.
t HD
DATAIN VALID
Document #: 38-05280 Rev. **
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CY7C186
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[11,12,14]
tWC ADDRESS CE1 tSA CE2 tSCE2 tAW tHA tSCE1
WE tSD DATA I/O DATAIN VALID tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 14]
tWC ADDRESS CE1 CE2 tSCE1 tSCE2 tAW WE tSA tPWE
t SD
tHA
tHD
DATA I/O
NOTE 13 tHZWE
DATAIN VALID tLZWE
Notes: 14. If CE1 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05280 Rev. **
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CY7C186
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC , I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 ICC NORMALIZED I , I SB CC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 VCC =5.0V VIN =5.0V ICC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
SUPPLYVOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4
AA
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 NORMALIZED t AA 1.4 1.2 1.0 VCC =5.0V 0.8 0.6 -55
OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25C
1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0
25
125
SUPPLYVOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO 2.5 DELTA t AA (ns) 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0
AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
OUTPUT SINK CURRENT (mA)
NORMALIZED t
OUTPUT VOLTAGE (V) NORMALIZED I CC vs. CYCLE TIME 1.25 VCC =5.0V TA =25C VCC =0.5V 1.00
20.0 15.0 10.0 5.0 0.0 0 200 400 VCC =4.5V TA =25C
NORMALIZED I CC
25.0
0.75
600
800 1000
0.50 10
20
30
40
SUPPLYVOLTAGE(V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05280 Rev. **
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CY7C186
Truth Table
CE1 CE2 H X L L L X L H H H WE X X H L H OE X X L X H Input/Output High Z High Z Data Out Data In High Z Mode Deselect/Power-Down Deselect Read Write Deselect
Address Designators
Address Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 Address Function X3 X4 X5 X6 X7 Y1 Y4 Y3 Y0 Y2 X0 X1 X2 DIP Pin Number 2 3 4 5 6 7 8 9 10 21 23 24 25 TSOP Pin Number 11 12 13 14 15 16 17 18 19 32 2 3 4
Ordering Information
Speed (ns) 20 25 35 Ordering Code CY7C186-20PC CY7C186-20ZC CY7C186-25PC CY7C186-35PC Package Name P15 Z32 P15 P15 Package Type 28-Lead (600-Mil) Molded DIP 32-Lead Thin Small Outline Package 28-Lead (600-Mil) Molded DIP 28-Lead (600-Mil) Molded DIP Commercial Commercial Operating Range Commercial
Document #: 38-05280 Rev. **
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CY7C186
Package Diagrams
28-Lead (600-Mil) Molded DIP P15
51-85017-A
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
51-85056-*D
Document #: 38-05280 Rev. **
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C186
Document Title: CY7C186 8Kx8 Static RAM Document Number: 38-05280 REV. ** ECN NO. 114447 Issue Date 3/26/02 Orig. of Change DSG Description of Change Change from Spec number: 38-00240 to 38-05280
Document #: 38-05280 Rev. **
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